Verilog HDL, 2e
Fully updated for the latest versions of Verilog HDL, this complete reference progresses logically from the most fundamental Verilog concepts to today's most advanced digital design techniques.
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Verilog HDL, 2e
Fully updated for the latest versions of Verilog HDL, this complete reference progresses logically from the most fundamental Verilog concepts to today's most advanced digital design techniques. Written for both experienced students and newcomers, it offers broad coverage of Verilog HDL from a practical design perspective. One step at a time, Samir Palnitkar introduces students to gate, dataflow (RTL), behavioral and switch level modeling presents the Programming Language Interface (PLI) describes leading logic synthesis methodologies explains timing and delay simulation and introduces many other essential techniques for creating tomorrows complex digital designs. Palnitkar offers a wealth of proven Verilog HDL modeling tips and more than 300 fully-updated illustrations, examples and exercises. Each chapter contains detailed learning objectives and convenient summaries.
| Book | |
|---|---|
| Author | Palnitkar |
| Pages | 492 |
| Year | 2006 |
| ISBN | 9788177589184 |
| Publisher | Pearson |
| Language | English |
| Uncategorized | |
| Edition | 2/e |
| Weight | 550 g |
| Dimensions | 20.3 x 25.4 x 4.7 cm |
| Binding | Paperback |